NOTE: For anyone still following this blog, please note this has been moved to http://parallellagram.org/. I will seldom be posting reminders here, will not be updating content here, and will be pasting no further content.
Two weeks ago I posted Tutorial 2 here: http://parallellagram.org/parallella-fpga-tutorial-2:-axi4-interface-to-bram.
In this tutorial, I will cover the process of enabling an on-chip peripheral, connecting it to the EMIO interface, routing this through the FPGA, and connecting it to external pins. This requires reassigning pins which are currently assigned for GPIO. On the Linux side, we will update the device tree, and using a a breakout board (such as the Porcupine), do a loopback test to confirm the peripheral is both operational and connected to the outside world. Continue reading
This tutorial covers the generation of a new parallella project, and is required reading for any of the following projects – if you create your projects using a naive planAhead Save Project As, I believe you’re in for a world of hurt. Continue reading
In order to help get people get started with FPGA programming to make the most of their Parallella, I have created this tutorial as a quick introduction. It draws on other tutorial material out there – the only new thing is presenting it in a format relevant to the Parallella and parallella-hw repository. It is written for ISE WebPack (14.7), and not Vivado. Continue reading